1999年研究生黃冠寰以其在矩陣最佳化編譯器研究的博士論文獲得最佳博士論文獎佳作（中華民國資訊協會）
ICPP conference @ Valenciw, Spain
LCPC conference @ Washington D.C., USA
2002年碩士生游逸平(Compilers for Low-Power)獲得中華民國資訊協會最佳碩士論文佳作獎
2003年碩士生吳琦(Low power designs) 獲得清華大學電機資訊學院最佳碩士論文佳作獎
Power-aware Scheduling for Parallel Security Processors with Analytical Models,Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq-Kuen Lee, Wei-Kuan Shih, and Ting-Ting Hwang, LCPC 2004, West Lafayette, Indiana, USA Sep. 21-25, 2004
2004年碩士生洪明郁(pointer analysis for speculative multi-threading architectures) 獲得清華大學電機資訊學院最佳碩士論文佳作獎
經濟部一般型學界科專計畫 - 前瞻高效能低耗能之雙處理器系統技術研發三年計畫(Advanced System Designs for High-Performance and Low-Power Dual-Core Processors) 全程計畫經費$58,000,000 NTD. 因應未來多媒體通訊應用產品的趨勢，促成了PAC計畫的執行。而本計畫（學界科專）的目標充分支援PAC計畫的時程，並與工研院系統晶片技術發展中心與電通所密切合作。本學界科專計畫包含三大分項：平行訊號處理器晶片之開發與電路設計、最佳化系統軟體開發工具組與相關函式庫之設計與實作、即時作業系統與應用軟體之研發與建構。本計畫以未來影音多媒體之行動通訊設備、資訊家電等嵌入式系統為應用，高效能與低耗能之系統特色為主要目標，開發先進的雙核心處理器系統之完整解決方案，並以此發展硬體/軟體之規劃、設計、系統整合、偵錯、驗證與測試等先進技術，推廣Hardware/Software Co-design之相關發展流程與概念，進一步建立國內獨立研發系統之完整解決方案的能力。
Efficient Switching Supports of Distributed .NET Remoting with Network Processors Chung-Kai Chen, Yu-Hao Chang, Cheng-Wei Chen, Yu-Tin Chen, Chih-Chieh Yang, Jenq-Kuen Lee
"A Sink-N-Hoist Framework for Leakage Power Reduction," Yi-Ping You, Chung-Wen Huang, Jenq-Kuen Lee
Compiler Supports and Optimizations for PAC VLIW DSP Processors Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Yu Hung, Yi-Ping You, Ya-Chiao Moo, Sheng-Yuan Chen, and Jenq-Kuen Lee
Register Allocation for VLIW DSP Processors with Irregular Register Files , Yung-Chia Lin, Yi-Ping You and Jenq Kuen Lee, CPC 2006, Spain, Jan. 2006.
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors, Chi Wu, Chung-Ju Wu, Jenq-Kuen Lee, at The 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
2006年碩士生李嘉哲、楊智傑獲得中華民國資訊協會最佳碩士論文佳作獎
Copy Propagation Optimization for VLIW DSP Processors with Distributed Register Files, Chung-Ju Wu, Sheng-Yuan Chen, Jenq-Kuen Lee, at The 19th International Workshop on Languages and Compilers for Parallel Computing
研究生團隊謝坤員、黃彥淳、黃建今 獲得2007全國大學院校嵌入式軟體設計競賽系統軟體組特優(第一名)，題目: PAC DSP BIOS 的設計與驗證
A Local-Conscious Global Register Allocator for VLIW DSP Processors with Distributed Register Files, Chia Han Lu, Young-Jia Lin, Yi-Ping You, Jenq-Kuen Lee, CPC 2007 (Compilers for Parallel Computing 2007), Lisbon, Portugal
博士生游逸平得到中華民國資訊學會最佳博士論文獎(優勝)(題目: 低功率嵌入式處理器之編譯器最佳化研究Compiler Optimizations on Embedded Processors for Low Power)
碩士生黃建今得到中華民國資訊學會最佳碩士論文獎(優勝)(題目: 支援數位訊號處理器之微核心設計與雙核心開發環境Microkernel Design and Dual-core Supports for PAC VLIW DSP Processors)
Processor employing a power managing mechanism and method of saving power for the same
Kun-Yuan Hsieh, Yen-Chih Liu, Po-Wen Wu, Shou-Wei Chang, and Jenq Kuen Lee, Enabling Streaming Remoting on Embedded Dual-Core Processors, In Proceedings of the 37th International Conference on Parallel Processing (ICPP ‘08), pp. 35-42, Portland, Oregon, September 8-12, 2008.
研究生團隊(王紹仲、陳亦廷、呂威儀)獲得2008教育部全國大學院校嵌入式軟體設計競賽「創意應用組佳作」(題目：棒球比賽轉播機器人)
研究生團隊(呂佳翰、關啟邦、林士涵)獲得2008教育部全國大學院校嵌入式軟體設計競賽「系統軟體組特優」(題目：PACDSP編譯器的設計與實作)
Chi-Hua Lai, Kun-Yuan Hsieh, Shang-Hong Lai, Jenq Kuen Lee, Parallelization of Belief Propagation Method on Embedded Multicore Processors for Stereo Vision, in Proceedings of the 6th IEEE Workshop on Embedded System for Real-Time Multimedia(ESTIMedia ‘08), pp. 39-44, Organized as part of Embedded Systems Week 2008 under CODES-ISSS 2008, Atlanta, Georgia, U.S.A., 19-24 Oct. 2008.
“Expression Rematerialization for VLIW DSP Processors with Distributed Register File,” Chung-Ju Wu, Chia Han Lu, and Jenq Kuen Lee
Power-gating instruction scheduling for power leakage reduction
研究生團隊(賴婉淑、林哲生、李登碩)獲得全國大學院校嵌入式軟體設計競賽「開放原始碼組優等」(題目：異質多核心嵌入平台之串流開發環境與多工測試)
李政崑教授榮獲98年Google Research Award (entitled 「Innovative Embedded System Curriculum on Android Platforms」), 包含郭大維教授,賴尚宏教授,張智星教授,劉志尉教授等成員。
Configurable SID-based Multi-core Simulators for Embedded System Education, Chung-Wen Huang, Wei-Kuan Shih, Yarsun Hsu, Jenq-Kuen Lee Oct. 11-16, 2009. Grenoble, France.
經濟部一般型學界科專計畫 - 嵌入式異質多核心系統技術研發三年計畫(第2期) (System Software Designs for Heterogeneous Embedded Multicore Processors) 全程計畫經費 $64,000,000 NTD. 處理器架構成長至今，由於半導體製程、執行效能與功率消耗的問題，多核心的處理器設計，已經變成廠商目前最佳的解決方式。因此本計畫延續前期（前瞻高效能低耗能之雙處理器系統技術研發三年計畫）的計畫成果，並以異質多核心平台為基礎，由清大李政崑教授擔任總主持人並主持A分項負責多核心系統軟體技術，以及C分項進行前期及本期成果之推廣；由台大郭大維教授主持B分項研究團隊負責多核心作業系統技術。 本計畫以兩校聯合簽約方式進行，目的在於提升技術移轉件數與金額，使各校可依其校內行政程序申請，增加自主性及誘因。整個計畫將展示從硬體到軟體，從單獨程式到多工作業系統，從雙核心開發環境到多核心開發環境的研究成果。同時透過學界與業界的合作，提昇國內多核心系統設計產業的國際競爭能力。
Method for allocating registers for a processor
Roaming Method for Maintaining Connectivity Through Heterogeneous Wireless Networks, and System for Realizing the Same
"A Multi-core Software API for Embedded MPSoC Environments," Jia-Jhe Li, Shao-Chung Wang, Po-Chun Hsu, Po-Yu Chen, and Jenq Kuan Lee
Parallelization of Stereo Vision Applications on Embedded Multi-Core Platforms, Jenq-Kuen Lee
"SIMD Intrinsic Supports for VLIW DSP Processors with Distributed Register Files," Chi-Bang Kuan, Jenq Kuen Lee
Method for allocating registers using simulated annealing controlled instruction scheduling
Task Scheduling Method for Low Power Dissipation in a System Chip
Visit Google campus and Dr. Shih Wei Liao
博士生謝坤員得到中華民國資訊學會最佳博士論文獎(佳作)題目: 「嵌入式多核心架構上之程式設計模型及系統軟體」
李政崑教授獲得99年度經濟部大學產業經濟貢獻獎-產業深耕個人獎
大學部/研究生團隊(許博竣、王鈺晟、林佑臻、陳冠旬、張哲睿、鄭凱懋、廖威軒)獲得2010通訊大賽-Android使用者介面設計競賽優等獎(題目:跨平台3D互動雲端整合環境)
Multi-Thread Power-Gating Control Design
OpenCL Update: OpenCL Compiler for GPUs/DSPs Yu-Te Lin, Shao-Chung Wang, Ming-Yu Hung, Jia-Jhe Li, Jenq-Kuen Lee
"Support of C++ Compiler for Embedded Multicore DSP Systems," Jenq Kuen Lee, Chi-Bang Kuan
2011年碩士生陳柏聿得到中華民國資訊學會最佳碩士論文獎(佳作)題目: 「具功耗量測之嵌入式多核心系統模擬器」
OpenCL Compiler for Embedded Multi-Core DSP Systems Jia-Jhe Li, Chi-Bang Kuan, Tung-Yu Wu, Ming-Yu Hung, and Jenq Kuen Lee
Method for Copy Propagation for Distributed Register File Architectures
"A Functional Approach to Optimize SIMD Computations of OpenCL Programs", Yu-Te Lin, Chi-Bang Kuan, Shao-Chung Wang, and Jenq-Kuen Lee
Method of streaming remote procedure invocation for multi-core systems
Method for instruction pipelining on irregular register files
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